| 1. |
- Forsell, Martti, et al.
(författare)
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Networks on Chip : Approaches and Challenges
- 2004
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Ingår i: Research and Development Activities in Telecommunication Systems. - : VTT Electronics. ; , s. 55-61
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Bokkapitel (refereegranskat)
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| 2. |
- Jantsch, Axel, et al.
(författare)
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Networks on Chip
- 2001
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Ingår i: Workshop at the European Solid State Circuits Conference.
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Konferensbidrag (refereegranskat)
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| 3. |
- Kumar, Shashi, et al.
(författare)
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A network on chip architecture and design methodology
- 2002
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Ingår i: VLSI 2002. - : IEEE conference proceedings. - 0769514863 ; , s. 105-112
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Konferensbidrag (refereegranskat)abstract
- We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NOC), includes both the architecture and the design methodology. The NOC architecture is a m x n mesh of switches and resources are placed on the slots formed by the switches. We assume a direct layout of the 2-D mesh of switches and resources providing physical- architectural level design integration. Each switch is connected to one resource and four neighboring switches, and each resource is connected to one switch. A resource can be a processor core, memory, an FPGA, a custom hardware block or any other intellectual property (LP) block, which fits into the available slot and complies with the interface of the NOC. The NOC architecture essentially is the onchip communication infrastructure comprising the physical layer, the data link layer and the network layer of the OSI protocol stack. We define the concept of a region, which occupies an area of any number of resources and switches. This concept allows the NOC to accommodate large resources such as large memory banks, FPGA areas, or special purpose computation resources such as high performance multiprocessors. The NOC design methodology consists of two phases. In the first phase a concrete architecture is derived from the general NOC template. The concrete architecture defines the number of switches and shape of the network, the kind and shape of regions and the number and kind of resources. The second phase maps the application onto the concrete architecture to form a concrete product.
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| 4. |
- Soininen, Juha-Pekka, et al.
(författare)
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Extending Platform-Based Design to Network on Chip Systems
- 2003
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Ingår i: Proceedings of the International Conference on VLSI Design.
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Konferensbidrag (refereegranskat)abstract
- Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been proposed as backbones for billion-transistor ASICs. We present a novel layered backbone-platform-system (BPS) design methodology for development of network-on-chip based products. It combines and extends the distributed, parallel, embedded and platform-based design concepts in order to manage the diversity and complexity of NOCbased-systems. The reuse of communication principles in various platforms, the reuse of platforms in product differentiation, and system-level decision-support methods are the cornerstones of our methodology. The presented mappability estimation and workload simulations demonstrate the feasibility of such methods.
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